1. Field of Invention
The present invention relates to a chip and a method for manufacturing thereof. More particularly, the present invention relates to a wafer level array of chips and method thereof.
2. Description of Related Art
Wafer level packaging (WLP) is one of the integrated circuit (IC) packaging techniques. In WLP, packaging and testing processes are performed after all chips are fabricated on one semiconductor wafer. When the packaging and testing processes are completed, a cutting process is performed to separate the chips, which are fabricated on the semiconductor wafer. FIG. 1A is a top-view of a semiconductor wafer with a chip array and scribe lines. FIG. 1B is a portion of FIG. 1A. FIG. 1C is a cross-sectional view of AA′ line in FIG. 1B. As shown in FIG. 1A, chip packages 100 are fabricated on a semiconductor wafer 10, and then the chip packages 100 are separate by the cutting process cutting along the scriber lines SL disposed between the chip packages 100. As illustrated in FIG. 1B and FIG. 1C, an inter-chip trench 106 is disposed between two adjacent chip packages 100 on the semiconductor wafer 10. The inter-chip trench 106 is formed for a cutter to enter and separate those two adjacent chip packages 100. However, as integrated density of IC keeping increasing, available space for IC within the chip should be accordingly increased to avoid issues such as signal interference or shortage caused by excessive density of the IC.